Connection bit order between hierarchy

Hi Masaru,
 

Thank you for sharing the detailed description and QAR. There is no Quartus option to prevent this reversal.
 

After review, this behavior is caused by a mismatch between SystemVerilog packed array ordering and Block Design indexing.

• SystemVerilog buses follow a fixed MSB-to-LSB order
• Block Design treats signals as an indexed list of bits

Because of this difference, Quartus connects signals based on their position (index), which results in a reversed connection.
For example:

Block Design:

• inst0 → index 0 
  inst1 → index 1 
  inst2 → index 2 
  inst3 → index 3

SystemVerilog:

• Out = [3] [2] [1] [0]   MSB to LSB

Quartus maps by position:

index 0 → Out[3] 
index 1 → Out[2] 
index 2 → Out[1] 
index 3 → Out[0]
 

Resulting in:

inst0 → Out[3] 
inst1 → Out[2] 
inst2 → Out[1] 
inst3 → Out[0]
 

The recommended workaround is to explicitly reorder the bits in the top-level module: 
assign Out = {bdf_out[0], bdf_out[1], bdf_out[2], bdf_out[3]};
 

This manually restores the intended mapping. 
 

I have also attached back the QAR for your reference.

Best regards,
Zi Ying