Forum Discussion
Occasional ContributorConnection bit order between hierarchy
Hi Masaru,
Thank you for the clarification.
After confirming once again with the Altera design team using the original design along with the information from the additional forum link that have been provided, this issue has been identified as a known software bug. As BDF has been deprecated and is no longer supported in newer Quartus releases, no fix is planned for this issue.
Here are some of the suggested workaround you may work with:1. Avoid using .bdf files by converting them to Verilog or VHDL in Quartus Prime Standard Edition using File → Create/Update → Create HDL Design File from Current File, and then use the generated HDL files in Quartus Prime Pro.
2. Replace the SystemVerilog top-level module with a VHDL, AHDL, or BDF top-level design to avoid the bus-ordering issue.
3. Continue using your existing workaround with the streaming operator (<<) to resolve the bus ordering.
We understand this may not be the outcome you were hoping for, and we apologize for the inconvenience. Please feel free to reach out if you have any further questions or concerns. If there are no further questions or updates, we may proceed with closing the support ticket accordingly.
Best regards,
ZiYingE_Altera
ContributorHi Masaru,
Thank you for sharing the detailed description and QAR. There is no Quartus option to prevent this reversal.
After review, this behavior is caused by a mismatch between SystemVerilog packed array ordering and Block Design indexing.
- SystemVerilog buses follow a fixed MSB-to-LSB order
- Block Design treats signals as an indexed list of bits
Because of this difference, Quartus connects signals based on their position (index), which results in a reversed connection.
For example:
Block Design:
- inst0 → index 0
inst1 → index 1
inst2 → index 2
inst3 → index 3
SystemVerilog:
- Out = [3] [2] [1] [0] MSB to LSB
Quartus maps by position:
index 0 → Out[3]
index 1 → Out[2]
index 2 → Out[1]
index 3 → Out[0]
Resulting in:
inst0 → Out[3]
inst1 → Out[2]
inst2 → Out[1]
inst3 → Out[0]
The recommended workaround is to explicitly reorder the bits in the top-level module:
assign Out = {bdf_out[0], bdf_out[1], bdf_out[2], bdf_out[3]};
This manually restores the intended mapping.
I have also attached back the QAR for your reference.
Best regards,
Zi Ying
Occasional ContributorZi Ying,
Thank you for the information.
.Out({<<{Out}})
also works.
I have checked this workaround for two-dimensional packed array.
If the Block Design entry goes on, I am happy that altera would fix this issue.
Masaru
