New ContributorConbinational group instead of regestered group
Hi all,
I am new to FPGA and Quartus and just truing to work with it. I am using Quartus Prime Lite edition 22.1. on Win 10.
I write a sample module with 3 always block doing just simple stuff. As counter variables I assign reg[7:0] r_cnt...
but after 3 variables all other reg[] suddenly becomes combinational groups instead of registered like it was before so that u_cnt,b_cnt,l_cnt are regestered group and b_bit become combinational group and all variables that I am creatine going into combinational groups.
How one can fix this issue?
Here is the code:
module controller (
input clk,
input las_en,
input Rx,
output reg las1,
output reg las2,
output reg u_clk
);
reg[15:0] u_cnt;
reg[5:0] b_cnt;
reg[5:0] l_cnt;
reg[7:0] d_bit;
reg l_flg,Rx_flg;
reg[7:0] dat_in;
initial begin u_clk = 0; l_flg = 1;Rx_flg = 0; las1 = 0; b_cnt = 0;bit = 0; dat_in = 0; end
always @(posedge clk) begin // lasers pulse control
if (las_en & l_flg) begin
las1 = 1; las2 = 1;
l_flg = 0;
end
if(l_flg == 0)l_cnt = l_cnt + 1;
if(l_cnt == 25) begin
las1 = 0; las2 = 0;
l_cnt = 0;
l_flg = 1;
end
end
always @(posedge clk) begin // UART clk
if(Rx==0) Rx_flg = 1;
if(Rx_flg) begin
u_cnt = u_cnt+1;
if(u_cnt== 109) begin u_cnt = 0; u_clk = ~u_clk; b_cnt = b_cnt + 1;end
if(b_cnt== 18 ) begin b_cnt = 0; Rx_flg = 0; end
end
end
always @(posedge u_clk) begin
bit = bit + 1;
dat_in[bit] = Rx;
if(bit==10) bit = 0;
end
endmodule
