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VitPri's avatar
VitPri
Icon for New Contributor rankNew Contributor
3 years ago

Conbinational group instead of regestered group

Hi all, I am new to FPGA and Quartus and just truing to work with it. I am using Quartus Prime Lite edition 22.1. on Win 10. I write a sample module with 3 always block doing just simple stuff....
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 years ago

You are using bit_cnt as an index for dat_in, but the value of bit_cnt can become greater than 7 (the range you set for dat_in) because you are incrementing it up to 10 at max. So without compiling it myself, something is getting optimized or latched because of this. You probably are seeing warnings in the messages window about this. Can you post those warnings?