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VitPri's avatar
VitPri
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3 years ago

Conbinational group instead of regestered group

Hi all, I am new to FPGA and Quartus and just truing to work with it. I am using Quartus Prime Lite edition 22.1. on Win 10. I write a sample module with 3 always block doing just simple stuff....
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,

By adding output dat_in,

in the code, you would able to see the reg[7:0] bit and reg[7:0] dat_in check the image below:

Thanks,

Best Regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

  • VitPri's avatar
    VitPri
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi Sheng,

    Your advice worked very good. It fix problem. Now I can see everything like it was declared. Thanks a lot.

    But just for understanding - why regs was converted to combinational?