Compilation on quartus tool fails for encrypted verilog and verilog header files
Hi,
I am trying to compile the encrypted design [generated by synopsys designware core]. This design is encrypted.
Quartus tool is not able to compile this encrypted design.
Quartus Tool version used: 22.3
Below is the error displayed during compilation:
Error(13411): Verilog HDL syntax error at DW_apb_i2c_intctl.vp(1) near text ?', expecting 'class
Below are experiments done:
1] RTL files those are encrypted one had .v extension. Tried removing this and added as .vp
2] Added below code in .qsf file:
set_global_assignment -name SYSTEMVERILOG_FILE /home/projects/ace/build/ace_agib027_2023_01_05_04_43_47/design/dw_i2c/i2c/src_enc/DW_apb_i2c_intctl.vp
Still, the error is shown.
Can you guide, how to compile the encrypted design files using Quartus tool ?
Regards
Sneha