Compilation on quartus tool fails for encrypted verilog and verilog header files

Hi Richard,

I went through the document and video. It shows how to encrypt and decrypt the design using Intel Key.

My concern is different. The third party IP is from synopsys. It is already encrypted. So the Quartus is not able to compile it.

With Xilinx Vivado, in such cases, we can launch the Synplify pro. using Vivado and then such RTL which is encrypted one can be compiled and synthesized for a specific FPGA target family. Once synthesis is done, the netlist is used further in the main flow for compilation.

So I think similar process could be there with Quartus tool but I was not able to find the same ?

Is there an option to launch the third party synthesis process with third party tool such as synplify pro and target the process for a specific Intel FPGA family ? Then I could be at-least generate the netlist and then use it in main compilation flow.

Regards

Sneha