Forum Discussion

AMare2's avatar
AMare2
Icon for New Contributor rankNew Contributor
6 years ago

Compilation of design with Nios fails when adding Signaltap

Hi,

I am using Quartus Prime Lite 17.1 and have a design with Nios II e on a Max 10 FPGA. If I add a signaltap file to the design and try to compile I get the following errors:

Error (11176): Factory com.altera.sopcmodel.components.tclmodule.TclModuleFactory reading /db/ip/sld9c8762f3/alt_sld_fab_wrapper_hw.tcl exception com.altera.utilities.FileUtilities$AlteraIpException: alt_sld_fab_wrapper_hw.tcl

Error (11176): No component alt_sld_fab in /db/ip/sld9c8762f3/alt_sld_fab_wrapper_hw.tcl

Error (12154): Can't elaborate inferred hierarchy "sld_hub:auto_hub".

Does anyone know what the alt_sld_fab_wrapper_hw.tcl is and from where is it coming?

I also noticed that 2 other things cause the same problem when compiling: adding the JTAG UART to the system in Platform Designer or selecting the "Include JTAG Debug" option of Nios II.

Could this be a license problem?

Thanks in advance.

8 Replies

  • AMare2's avatar
    AMare2
    Icon for New Contributor rankNew Contributor
    6 years ago

    Thank you for the tips.

    I have finally found the problem. It was a non-English character in the folder name of the project! I am not sure why this caused a problem with Signaltap only but by coincidence I noticed that the project including Signaltap would run successfully if I copied the project to another folder so I tried changing the folder name and it worked.

    • RRomano001's avatar
      RRomano001
      Icon for Contributor rankContributor
      6 years ago

      Hi Amare, try compare the xml code on .qsys file, sometimes help you track why fail. this must be responsibility of Altera (now intel) to produce a quality software. Seems they use M$ market strategy to use customer as free beta tester.

      They forgot this is not a PC computer product and cannot be sold uncertified.

      I found some issue coming from these files, I found something general about path are stored as M$ mode absolute path... Bad practice to be avoided.

      About character I think you are on win platform, if so some character like "&" on filename (or dir aka folder name) i learnt in the past can generate catastrofic failure on disk storage too.

      We are here to see if Altera (Now intel) grasp the importance of what was bought or simply leave in it agony to death.

      (Edit: Many of these issue are present from long long time ago and never addressed. Example linux PLL issue appeared 2015)

      Regard.

      Roberto

    • AnandRaj_S_Intel's avatar
      AnandRaj_S_Intel
      Icon for Regular Contributor rankRegular Contributor
      6 years ago

      ​Hi,

      Intel Altera only supports standard alphanumeric characters and underscores (_) in installation paths and project directory.

      Examples of unsupported characters: \/:*?"<>|!£$%^&()

      Regards

      Anand

      • RRomano001's avatar
        RRomano001
        Icon for Contributor rankContributor
        6 years ago

        Hi Anand, a parser to pinpoint wrong path is not so difficult to write, at almost jut test path string. Not forever just when path var is created.

        About catastrophic "&" behavior appear just on windows OS, Unix, Linux too accept also control character on path/file name. It is good taste of user not to do.

        If \ / character are not supported, how can we specify path?? Maybe one of two can be confused with escape sequences, but on path one of this is a standard.

        It is better prevent what can hurt code than leaving untested and not clearly stated

        Regards

        Roberto.

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    6 years ago

    Double-check that you've selected the Nios /e version instead of /f which does require licensing.

    Are you saying that if you have Nios in a design with the JTAG debug option on but no Signal Tap you still have the same issue? Basically, is there any setup (say, with no JTAG features enabled) that allows you to successfully compile?

    #iwork4intel

  • RRomano001's avatar
    RRomano001
    Icon for Contributor rankContributor
    6 years ago

    Hi, one of too many issue I noticed is on save.

    Try reopen Qsys, remove IP NIOS, UART and JTAG Debug.

    Reinsert IP connect then save twice before generate.

    SOmetimes this solve these issue.

    If project isn't too large, try create a new one, then reload IP and don't forget double save qsys before generate.

    regards

  • AMare2's avatar
    AMare2
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi,

    Thanks for your replies.

    I have tried to remove the IPs and regenerate, I also tried to create a new design, I tried the double save then regenerate, and still I get the same error.

    I have also created a new design that has nothing but Nios and an Onchip Memory and still I get the same errors if I have Signaltap or the JTAG Debug option.

    The compilation works only if all 3 (JTAG Debug option, UART JTAG, Signaltap) are removed.

    Any ideas?

    Thanks a lot.

    • AnandRaj_S_Intel's avatar
      AnandRaj_S_Intel
      Icon for Regular Contributor rankRegular Contributor
      6 years ago

      Hi,

      In your project, run Analysis & Synthesis, and then view the report->Analysis & Synthesis->IP Cores Summary report.

      This report displays the name, vendor, version, license type, and other data about the IP cores in your project. Which will help us in finding the license issues.

      1. delete db and incremental_db folders.
      2. create new stp file and check.

      Regards

      Anand