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AMare2's avatar
AMare2
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6 years ago

Compilation of design with Nios fails when adding Signaltap

Hi, I am using Quartus Prime Lite 17.1 and have a design with Nios II e on a Max 10 FPGA. If I add a signaltap file to the design and try to compile I get the following errors: Error (11176): Facto...
AMare2's avatar
AMare2
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6 years ago

Thank you for the tips.

I have finally found the problem. It was a non-English character in the folder name of the project! I am not sure why this caused a problem with Signaltap only but by coincidence I noticed that the project including Signaltap would run successfully if I copied the project to another folder so I tried changing the folder name and it worked.

RRomano001's avatar
RRomano001
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6 years ago

Hi Amare, try compare the xml code on .qsys file, sometimes help you track why fail. this must be responsibility of Altera (now intel) to produce a quality software. Seems they use M$ market strategy to use customer as free beta tester.

They forgot this is not a PC computer product and cannot be sold uncertified.

I found some issue coming from these files, I found something general about path are stored as M$ mode absolute path... Bad practice to be avoided.

About character I think you are on win platform, if so some character like "&" on filename (or dir aka folder name) i learnt in the past can generate catastrofic failure on disk storage too.

We are here to see if Altera (Now intel) grasp the importance of what was bought or simply leave in it agony to death.

(Edit: Many of these issue are present from long long time ago and never addressed. Example linux PLL issue appeared 2015)

Regard.

Roberto