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AMare2's avatar
AMare2
Icon for New Contributor rankNew Contributor
6 years ago

Compilation of design with Nios fails when adding Signaltap

Hi, I am using Quartus Prime Lite 17.1 and have a design with Nios II e on a Max 10 FPGA. If I add a signaltap file to the design and try to compile I get the following errors: Error (11176): Facto...
AMare2's avatar
AMare2
Icon for New Contributor rankNew Contributor
6 years ago

Hi,

Thanks for your replies.

I have tried to remove the IPs and regenerate, I also tried to create a new design, I tried the double save then regenerate, and still I get the same error.

I have also created a new design that has nothing but Nios and an Onchip Memory and still I get the same errors if I have Signaltap or the JTAG Debug option.

The compilation works only if all 3 (JTAG Debug option, UART JTAG, Signaltap) are removed.

Any ideas?

Thanks a lot.

  • AnandRaj_S_Intel's avatar
    AnandRaj_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    In your project, run Analysis & Synthesis, and then view the report->Analysis & Synthesis->IP Cores Summary report.

    This report displays the name, vendor, version, license type, and other data about the IP cores in your project. Which will help us in finding the license issues.

    1. delete db and incremental_db folders.
    2. create new stp file and check.

    Regards

    Anand