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AMare2's avatar
AMare2
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6 years ago

Compilation of design with Nios fails when adding Signaltap

Hi, I am using Quartus Prime Lite 17.1 and have a design with Nios II e on a Max 10 FPGA. If I add a signaltap file to the design and try to compile I get the following errors: Error (11176): Facto...
RRomano001's avatar
RRomano001
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6 years ago

Hi, one of too many issue I noticed is on save.

Try reopen Qsys, remove IP NIOS, UART and JTAG Debug.

Reinsert IP connect then save twice before generate.

SOmetimes this solve these issue.

If project isn't too large, try create a new one, then reload IP and don't forget double save qsys before generate.

regards