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AMare2's avatar
AMare2
Icon for New Contributor rankNew Contributor
7 years ago

Compilation of design with Nios fails when adding Signaltap

Hi, I am using Quartus Prime Lite 17.1 and have a design with Nios II e on a Max 10 FPGA. If I add a signaltap file to the design and try to compile I get the following errors: Error (11176): Facto...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
7 years ago

Double-check that you've selected the Nios /e version instead of /f which does require licensing.

Are you saying that if you have Nios in a design with the JTAG debug option on but no Signal Tap you still have the same issue? Basically, is there any setup (say, with no JTAG features enabled) that allows you to successfully compile?

#iwork4intel