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davidyu1's avatar
davidyu1
Icon for New Contributor rankNew Contributor
2 years ago

Compilation fail duo to hps_csdram_p0

We used platform designer and use hps IP to build our design.

But Compilation failed and had the following message:

Error: The auto-constraining script was not able to detect any instance for core < hps_sdram_p0 >
Error: Verify the following:
Error: The core < hps_sdram_p0 > is instantiated within another component (wrapper)
Error: The core is not the top-level of the project
Error: The memory interface pins are exported to the top-level of the project
Error: Alternatively, if you are no longer instantiating core < hps_sdram_p0 >,
Error: clean up any stale SDC_FILE references from the QSF/QIP files.

How to solve this issue?

12 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    Is this a golden reference design you downloaded or something you created yourself? Can you show the Platform Designer system design (.qsys)?

  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi davidyu1,


    Do you still require help regarding this issue?


    Thanks.

    Regards,

    Aik Eu


  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi davidyu1,


    May I know which document which you refer to build your project?

    The original ghrd used was working fine without compilation issue or after you modify it only got issue?


    Thanks.

    Regards,

    Aik Eu


    • davidyu1's avatar
      davidyu1
      Icon for New Contributor rankNew Contributor
      2 years ago
      Hi Aik Eu,
      I created new project with your de10-nano template file(DE10_Nano_golden_top.qar) and use platform designer to add hps-to-fpga interface in my design.
      You can see my project files I attached the post previously.
      I found that the compilation issue is from adding hps-to-fpga interface.
      If I remove hps-to-fpga interface from qsys, the compilation is without error.
    • davidyu1's avatar
      davidyu1
      Icon for New Contributor rankNew Contributor
      2 years ago

      Hi Aik Eu,

      When I followed these steps from the link you metioned, running hps_sdram_p0_pin_assignments.tcl had the similar error.

      I have attached the screen shot file to the post.

      Thanks.

      Regards,

      David Yu

  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi davidyu1,


    I understand that you have modified the golden design example of DE10 nano. I not very sure the problem from your modification other than adding additional soft IP which connect to the bridge.

    Anway can try run with other example like from previous link or any example which uses a PIO controller IP:

    https://www.rocketboards.org/foswiki/Documentation/SoCEDS

    From there only add on your modification.


    Thanks.

    Regards,

    Aik Eu


  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi davidyu1,


    I am closing this thread now. Do consider re-open a new thread after you have tried the compilation with a working pio design example.


    Thanks.

    Regards,

    Aik Eu


  • anonimcs's avatar
    anonimcs
    Icon for Contributor rankContributor
    1 year ago

    Hi,

    I'm not using a golden ref design but I have similar errors at the fitter stage (I'm using Quartus 17.1 Standard on Ubuntu 20.04). I tried removing the db/ and incremental_db/ folders and the run a full compilation as well, but it didn't help. If anyone knows the fix, that'd be great to find out.

    Cheers