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5 Replies
- Altera_Forum
Honored Contributor
I would have thought, that depends on how you right the testbench. You should generate test cases that should exercise all parts of the design, maybe even move into constrained random testing.
I dont understand what you mean by "single instruction", and "calls a module". There are no instructions in VHDL, and you cannot "call" a module. Components are instantiated, functions are called. - Altera_Forum
Honored Contributor
Hi Tricky,
in fact a function is called: "wait;" . Here's a part of code:
instead I want to cover all the "PeriodMeter" code How can I do?library ieee; use ieee.std_logic_1164.all; ... entity testbench is generic( ... ); end testbench; architecture arch of testbench is signal reset : std_logic; begin the_reset_sim : RESET_SIM -- RESET_SIM instance generic map ( WIDTH=>100 ) port map ( reset_o=>reset ); PeriodMeter : period_meter --my module instance generic map ( PULSE_CNT_BITS=>PULSE_CNT_BITS, TIME_CNT_BITS=>TIME_CNT_BITS, PRESCALE_VAL=>PRESCALE_VAL ) port map ( clk_i=>o_clk, reset_i=>reset, in_i=>o_clk, d_o=>o_register ); SimProcess : process begin wait; -- this is the only one function called end process SimProcess; end arch; - Altera_Forum
Honored Contributor
this code does nothing. The wait you see just tells the process to halt (because a process is just a never-ending loop).
You will need to generate a reset and clock in the testbench to stimulate the period meter, along with any other inputs. - Altera_Forum
Honored Contributor
What compilation options are you using in Modelsim? I think that code coverage will probably be disabled if optimizations are enabled during the compilation.
I've never used code coverage in Modelsim (the version distributed with Quartus doesn't include that) but maybe you'll find more information about that in the manual. - Altera_Forum
Honored Contributor
You have to enable code coverage for your unit/device under test (in your case "period_meter") if you want to see if these are covered. A 100% code coverage of your testbench just tells you that all instructions in your testbench are executed but not what coverage your unit under test has.
As Tricky said already you need to generate a stimulus for your unit under test or you will get 0% coverage for your component.