Code Coverage: covering a module within testbench

Hi Tricky,

library ieee;
use ieee.std_logic_1164.all;
...
entity testbench is
  generic(
      ...
  );
end testbench;
architecture arch of testbench is
  signal   reset    : std_logic;  
begin
    the_reset_sim : RESET_SIM        -- RESET_SIM instance
        generic map
        (
            WIDTH=>100
        )
        port map
        (
            reset_o=>reset
        );
    PeriodMeter : period_meter        --my module instance
                generic map
                (
                    PULSE_CNT_BITS=>PULSE_CNT_BITS,
                    TIME_CNT_BITS=>TIME_CNT_BITS,
                    PRESCALE_VAL=>PRESCALE_VAL
                )
                port map
                (
                    clk_i=>o_clk,
                    reset_i=>reset,
                    in_i=>o_clk,
                    d_o=>o_register
     );
    SimProcess : process
        
    begin
        wait;                 -- this is the only one function called
    end process SimProcess;
    
end arch;