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Altera_Forum
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14 years ago

Code Coverage: covering a module within testbench

Hi all, making the code coverage with Modelsim on my VHDL testbench, the result is 100%, but only a single instruction is covered, which is the one that calls the sub-module within the testbenc...
Altera_Forum's avatar
Altera_Forum
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14 years ago

I would have thought, that depends on how you right the testbench. You should generate test cases that should exercise all parts of the design, maybe even move into constrained random testing.

I dont understand what you mean by "single instruction", and "calls a module". There are no instructions in VHDL, and you cannot "call" a module. Components are instantiated, functions are called.