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Altera_Forum
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14 years ago

Code Coverage: covering a module within testbench

Hi all, making the code coverage with Modelsim on my VHDL testbench, the result is 100%, but only a single instruction is covered, which is the one that calls the sub-module within the testbenc...
Altera_Forum's avatar
Altera_Forum
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14 years ago

this code does nothing. The wait you see just tells the process to halt (because a process is just a never-ending loop).

You will need to generate a reset and clock in the testbench to stimulate the period meter, along with any other inputs.