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Mikexx's avatar
Mikexx
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Clock missing from Timing Analyzer - Report Setup Summary

I have a clock mux along the lines in "ug-qps-03-design-recommendations.pdf" I have set the output clock to be a Global Clock in the Assignment Editor and I give it's minimum period in the sdc file....
Timing
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,

I had checked the design. Since HDMI_TX_CLK is not source-synchronous, so you wouldn't see the setup and hold.

You can report the delay by Report Path... From put * and To put [get_keepers {HDMI_TX_CLK}] then you'll see the result like below:

Thanks,

Regards,

Sheng

  • Mikexx's avatar
    Mikexx
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Many thanks for looking into this. And apologies for the delay due to personal commitments.

    I'm a little confused as other clock signals are global and also generated from a PLL and yet are listed in the setup and old times.

    My understanding of a source synchronous system is when the signal source is clocked by a different clock to the destination register?

    The design has many registers that are clocked by a global clock, ie a common clock, in this case HDMI_TX_CLK aka TX_PCLK and therefore should all have a common clock topology?