Clock has no driving source

Yes you got it right. QSys assembles components in a big component, but you usually still have a "top level" file (VHDL, Verilog, or schematic) that connects this big component to FPGA pins. There are actually three reasons to do that[list][*]being able to change pin names[*]add external components (I usually like to keep my plls outside of the QSys project for example)[*]adapt some external interfaces to your board. Examples include RAM address bus adjustment, chip select polarities, or interface conversion. There are a few things you need to be able to do outside of QSys[/list]

You can do a schematic top level file from Quartus directly. Create a new schematic, declare it as top level and put the QSys component in there. That said I would really recommend you to use HDL instead,either Verilog of VHDL. You think that you gain some time by using schematics, but it isn't true in the long run. Schematics are harder to maintain, and Quartus has the nasty habit of shuffling all the pins on the symbols each time you make a change to a component, so each time you'll do a change to the QSys system, you'd have to redo a lot of connections on the schematic. HDL are easier to use in this case, once you get used to it.

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I’m new to Altera tools and I am struggling to get a understanding of the overall flow of Quartus.

I'm trying to get a Demo (BeMicro_SDK_Embedded_System_HW_Lab_QSys.pdf) from Arrow that uses a BeMicro development board working.

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http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial

Go through this SOPC/Qsys tutorial. It has a BeMicro and BeMicro-SDK example.

Cheers,

Dave

So Daixiwen I am very interested to know why you keep your PLLs out of Qsys??

I am not surprised how the pins changing thing is a hassle but I’m more surprised there is no tcl script way to keep them straight.

The last time I programmed hardware it was PALASM, ABEL and UV erasable 22V10.

Even though I wrote the code first, I always drew schematics for the programmers and anyone else that I need to explain how things worked for documentation reasons.

It made life easier for everyone involved especially me.

It is really not helpful when the repair/service/assembly technician opens the schematic of the device and there is an abstract block defined by some programming which he doesn’t understand but he does know what a register is and combinatorial logic should do.

I already wish it were different??

Seems to me that Qsys should be able to make a schematic on its own from the VHDL/Verilog if the component had a drawing/graphical object (for lack of a better term) with the pins defined??

Seems like when you “connect things in VHDL a schematic should fall out of that process if the graphical/drawing information existed in the model for that component.

Are you saying that there is not a way to attach a graphical representation to a VHDL/Verilog component because the canned ones from Altera have this even though I suspect/assumed somewhere is a VHDL description underneath the covers somewhere?

So can you see from the “big daddy”/project VHDL file why my clock pin is not connected?

In Quartus if I go to assignments and search for pin E1 I can see it is connected to signal name CLK_FPGA_50M.

Okay fair enough.

I would assume that the pinassignment.tcl script made this assignment from the statement “set_location_assignment PIN_E1 -to CLK_FPGA_50M”

Okay that signal name is assigned to the E1 pin where it should be but I still don’t understand/have no clue how to connect/tie together CLK_FPGA_50M signal to my clk_in input of my clock source component in Qsys.

Seems to me there should be a way/method (I can’t find an example or I am reading over it) to say assign this signal from pin E1 in this case “CLK_FPGA_50M” so it connects to this component in this case my clock source named “ext_clk_50” and its input signal clk_in.

If fact what bothers me more is that in the pinassignment.tcl script I don’t recognize any of the signal names.

Yes I need a couple of buses for the ddram controller but that is not what it is called in my component …..in my component they are called porta and portb.

In the tcl script I have this nonsense set_location_assignment PIN_B3 -to RAM_A0 etc.(there is another statement that makes sense it defines what type of signal/what type of pin to use set_instance_assignment -name IO_STANDARD "1.8 V" -to RAM_A0).

Seems like I have two names for everything how is this helpful?

What purpose does it serve to call the pin something other than what it’s called on the component?.

If I were doing it you would assign the pin the name to a signal of the component like componentname.signalname.

So in my case I would do a command that would look like this set_location_assignment PIN_E1 to ext_clk_50.clk_in.

Apparently (by looking at my big daddy VHDL file and the pinassignment.tcl fil) this double naming is going on everywhere but why would you do his even if you could?

You need to do the connection inside your verilog top level file. Create an input wire called CLK_FPGA_50M and assign it to the pin ext_clk_50 inside the nios2_bemicro_system component instantiation.

For the PLLs I usually create them with the Megawizard and instantiate them in a separate block called "clocks" that I instantiate in the top level file.

Quartus does generate graphical descriptions of what it is doing. QSys generates an html file with an almost human readable representation of your system, the different connections made between the components and an address map. The Quartus synthesizer also generates an almost human unreadable representation of all the logic inside the FPGA: the RTL viewer. But you will soon realize that the systems we design today are too complex for a computer to try and generate a nice graphical representation.

Hi Daixiwen

Thanks for the reply.

I hope I don’t come across as ungrateful (believe me I very much appreciate your help) but there wasn’t much information in your answer.

I believe you when you say you put your PLLs outside of Qsys but why do you do this?

How does one make an assignment and reference a Qsys component and signal of that component?

I’ve been watching VHDL tutorials and reading VHDL books but there is no mention of this that I can find anywhere.

Once I make the assignment how does Qsys become aware that the VHDL file has been changed so I can compile my project ?

Is there a recompile of something needed???………………………….obviously I don’t understand the communication/interface between Qsys and the project/ big daddy VHDL file very well/ at all.

The project/ big daddy VHDL file does assign the pin to a wire and then to a signal name(CLK_FPGA_50M) but I still have no idea why/what purpose the double naming serves?????

Why wouldn’t one just use the name of the component and the signal name?......maybe this is why my demo won’t compile.

'To' name unrecognized EXT_CLK_50 Location PIN_E1 Yes \\this is from the assignment editor

input wire CLK_FPGA_50M \\ this is from the project VHDL file

My trouble is that my clock source has component name and a signal name how do you reference the signal name and the component name?

You should look for a tutorial about hierarchical design (and maybe in Verilog rather than VHDL, as your top level file is in Verilog right now).

Basically all the lines between

// Qsys system
nios2_bemicro_system u0 (

and

);

are assignments, connections between a port on the QSys component and a port on the top level verilog file (that are also FPGA pins). For example this line

.mobile_ddr_sdram_external_CKE (RAM_CKE), // .CKE

says the QSys mobile_ddr_sdram_external_CKE port to the FPGA port RAM_CKE.

In your case you'll probably need to add something like

.CLK_FPGA_50M(EXT_CLK_50),

You don't need to do anything to make Quartus aware you made a change. When yo compile your project it will look into all your files. If there is a problem when trying to connect together your QSys project and the top level file then you'll get an error.