Clock has no driving source

You need to do the connection inside your verilog top level file. Create an input wire called CLK_FPGA_50M and assign it to the pin ext_clk_50 inside the nios2_bemicro_system component instantiation.

For the PLLs I usually create them with the Megawizard and instantiate them in a separate block called "clocks" that I instantiate in the top level file.

Quartus does generate graphical descriptions of what it is doing. QSys generates an html file with an almost human readable representation of your system, the different connections made between the components and an address map. The Quartus synthesizer also generates an almost human unreadable representation of all the logic inside the FPGA: the RTL viewer. But you will soon realize that the systems we design today are too complex for a computer to try and generate a nice graphical representation.