Clock has no driving source

You should look for a tutorial about hierarchical design (and maybe in Verilog rather than VHDL, as your top level file is in Verilog right now).

Basically all the lines between

// Qsys system
nios2_bemicro_system u0 (

and

);

are assignments, connections between a port on the QSys component and a port on the top level verilog file (that are also FPGA pins). For example this line

.mobile_ddr_sdram_external_CKE (RAM_CKE), // .CKE

says the QSys mobile_ddr_sdram_external_CKE port to the FPGA port RAM_CKE.

In your case you'll probably need to add something like

.CLK_FPGA_50M(EXT_CLK_50),

You don't need to do anything to make Quartus aware you made a change. When yo compile your project it will look into all your files. If there is a problem when trying to connect together your QSys project and the top level file then you'll get an error.