Honored Contributor
Honored ContributorHi Daixiwen
Thanks for the reply. I hope I don’t come across as ungrateful (believe me I very much appreciate your help) but there wasn’t much information in your answer. I believe you when you say you put your PLLs outside of Qsys but why do you do this? How does one make an assignment and reference a Qsys component and signal of that component? I’ve been watching VHDL tutorials and reading VHDL books but there is no mention of this that I can find anywhere. Once I make the assignment how does Qsys become aware that the VHDL file has been changed so I can compile my project ? Is there a recompile of something needed???………………………….obviously I don’t understand the communication/interface between Qsys and the project/ big daddy VHDL file very well/ at all. The project/ big daddy VHDL file does assign the pin to a wire and then to a signal name(CLK_FPGA_50M) but I still have no idea why/what purpose the double naming serves????? Why wouldn’t one just use the name of the component and the signal name?......maybe this is why my demo won’t compile. 'To' name unrecognized EXT_CLK_50 Location PIN_E1 Yes \\this is from the assignment editor input wire CLK_FPGA_50M \\ this is from the project VHDL file My trouble is that my clock source has component name and a signal name how do you reference the signal name and the component name?
