Clock has no driving source

Yes you got it right. QSys assembles components in a big component, but you usually still have a "top level" file (VHDL, Verilog, or schematic) that connects this big component to FPGA pins. There are actually three reasons to do that[list][*]being able to change pin names[*]add external components (I usually like to keep my plls outside of the QSys project for example)[*]adapt some external interfaces to your board. Examples include RAM address bus adjustment, chip select polarities, or interface conversion. There are a few things you need to be able to do outside of QSys[/list]

You can do a schematic top level file from Quartus directly. Create a new schematic, declare it as top level and put the QSys component in there. That said I would really recommend you to use HDL instead,either Verilog of VHDL. You think that you gain some time by using schematics, but it isn't true in the long run. Schematics are harder to maintain, and Quartus has the nasty habit of shuffling all the pins on the symbols each time you make a change to a component, so each time you'll do a change to the QSys system, you'd have to redo a lot of connections on the schematic. HDL are easier to use in this case, once you get used to it.