Honored ContributorHi everyone,
I'm asking how can I produce a time delay for exemple, I want to put a pin to the ground, then 1s later, I wanna put the second pin to the ground I was exemple of program like after or wait. But it seems I used them badly, it doesn't really work with me Could anyone help me please? thank you very much
Honored Contributorwait statements are only for simulation. If you want to synthesize your design you will have to create counters, which you check and based on their value you either bring a signal high or low.
Honored ContributorHere is the synthesizeable code would help :
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity delay_gen is ( nreset : in std_logic; clock : in std_logic; pin1 : out std_logic; pin2 : out std_logic ); end entity delay_gen; architecture behav of delay_gen is type simple_fsm is (st1, st2); signal state_trans : simple_fsm; signal sec_count : std_logic_vector(10 downto 0); begin delay_proc: process(nreset,clock) begin if(nreset = '0') then state_trans <= st1; sec_count <= (others=>'0'); elsif(rising_edge(clock)) then case state_trans is when st1 => pin1 <= '0'; -- Set to ground sec_count <= x""; --Put the counter value w.r.t to the clock you select state_trans <= st2; when st2 => if(sec_count > 0) then --1 second counter has not elapsed sec_count <= sec_count - 1; --decrement counter state_trans <= state_trans; --continue to be there in same state else pin2 <= '0'; -- Set second pin to ground state_trans <= st1; end if; when others => sec_count <= x"" --Put the counter value w.r.t to the clock you select pin1 <= '1'; --Keep pin1 at VCC pin2 <= '1'; --Keep pin1 at VCC end case; end if; end process delay_proc; end architecture behav;Honored ContributorThank you for your replying, but it seems I met some problem with that code, what should I put instead of x""? I put 1000 instead and it doesn' work
Honored Contributor
