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sth125's avatar
sth125
Icon for New Contributor rankNew Contributor
2 years ago
Solved

Clock constraints specified in sdc file reset by compilation process

Hello, I am using Quartus Prime Lite Edition to compile logic for a MAX V 5M1270ZT144C4 CPLD. I created an sdc file that contained a constraint for only 1 clock, i.e. create_clock -name {CLK1} -pe...
Compilation
Hdl
Timing
  • sth125's avatar
    sth125
    2 years ago

    I solved the issue.

    I just needed to add the sdc file in my project. I had thought it would automatically include it.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

As you discovered, if no clock constraints are found, all clocks default to 1 GHz, which is basically useless. Glad you figured out the issue.