Forum Discussion
sth125
New Contributor
New ContributorClock constraints specified in sdc file reset by compilation process
Hello, I am using Quartus Prime Lite Edition to compile logic for a MAX V 5M1270ZT144C4 CPLD. I created an sdc file that contained a constraint for only 1 clock, i.e. create_clock -name {CLK1} -pe...
I solved the issue.
I just needed to add the sdc file in my project. I had thought it would automatically include it.
sstrell
Super Contributor
Super ContributorAs you discovered, if no clock constraints are found, all clocks default to 1 GHz, which is basically useless. Glad you figured out the issue.
