Checker not found - Verilog.

Hey i wrote this code in Verilog.

This is the Code:

module shift_register(write,s_in,clk,d,s_out,p);

input write,clk;

input [3:0] d;
input [11:0] s_in;

output reg s_out;
output reg [3:0] p;

wire mux_1,mux_2,mux_3,mux_4,dff_1,dff_2,dff_3,dff_4; // 8 wires

mux2_1 mux1(.s(s_in),.d(d[3]),.w(write),.z(mux_1)); // mux1

D_FlipFlop dff1(.d(mux_1),.clk(clock),.q(dff_1)); // DFlipFlop1
always@(posedge clk) begin
p[3]<=dff_1;
end
mux2_1 mux2(.s(dff_1),.d(d[2]),.w(write),.z(mux_2));// mux2

D_FlipFlop dff2(.d(mux_2),.clk(clock),.q(dff_2));  // DFlipFlop2
always@(posedge clk) begin
p[2]<=dff_2;
end
mux2_1 mux3(.s(dff_2),.d(d[1]),.w(write),.z(mux_3));// mux3

D_FlipFlop dff3(.d(mux_3),.clk(clock),.q(dff_3));  // DFlipFlop3
always@(posedge clk) begin
p[1]<=dff_3;
end
mux2_1 mux4(.s(dff_3),.d(d[0]),.w(write),.z(mux_4));// mux4

D_FlipFlop dff4(.d(mux_4),.clk(clock),.q(dff_4));  // DFlipFlop4
always@(posedge clk) begin
p[0]<=dff_4;

s_out<=dff_4;
end
endmodule

and this is the Testbench:

module shift_register_testbench();
wire write,clk;

input [3:0] d;
input [11:0] s_in;

output reg s_out;
output reg [3:0] p;

 initial
 begin 
d[3:0]  = 1'b1;
write = 1'b0;

s_in[0] = 1'b1;
#10;
s_in[1] = 1'b0;
#10;
s_in[2] = 1'b0;
#10;
s_in[3] = 1'b1;
#10;
s_in[4] = 1'b0;
#10;
s_in[5] = 1'b0;
write = 1'b1;
#10;
s_in[6] = 1'b1;
write = 1'b0;
#10;
s_in[7] = 1'b0;
#10;
s_in[8] = 1'b1;
#10;
s_in[9] = 1'b1;
#10;
s_in[10] = 1'b1;
#10;
s_in[11] = 1'b0;
#10;


shift_register SRTB(.write(write),.s_in(s_in[11:0]),.clk(clk),.d(d[3:0]),.s_out(s_out),.p(p[3:0]));

end
endmodule

And when I`m try to run the testbench this problem appear:

how can i fix it?THNX!