VerilogStudentNew Contributor6 years agoChecker not found - Verilog. Hey i wrote this code in Verilog. This is the Code: module shift_register(write,s_in,clk,d,s_out,p); input write,clk; input [3:0] d; input [11:0] s_in; output reg s_out; output reg [3:0] p; ...Show More
Recent DiscussionsIs there any way to script the creation of a signal tap instance?MAX10 ADC - getting it to simulate in ModelsimQuartus 26.1: quartus_asm triggers quartus_pfg despite disabled generation flagsQuartus Lite 23.1 MAX 10 EncryptionCould not link 'vsim_auto_compile.dll' error troubleshooting.