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VerilogStudent's avatar
VerilogStudent
Icon for New Contributor rankNew Contributor
5 years ago

Checker not found - Verilog.

Hey i wrote this code in Verilog. This is the Code: module shift_register(write,s_in,clk,d,s_out,p); input write,clk; input [3:0] d; input [11:0] s_in; output reg s_out; output reg [3:0] p; ...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

Where is your shift register HDL file located? Is it in the same directory as the testbench? I think the issue is ModelSim is simply not seeing the file. Make sure you "Change Directory" in ModelSim to point to the location of the code.

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