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VerilogStudent
New Contributor
New ContributorChecker not found - Verilog.
Hey i wrote this code in Verilog.
This is the Code:
module shift_register(write,s_in,clk,d,s_out,p);
input write,clk;
input [3:0] d;
input [11:0] s_in;
output reg s_out;
output reg [3:0] p;
...
SyafieqS
Super Contributor
Super ContributorHi Naor,
Make sure your HDL and testbench in same directory when you simulating the design. The directory in Modelsim is same as the path where your hdl and tb files.
Thanks,
Regards
