check the verilog code of ADC on FPGA

hi all

when i assign LVDS pins to one IO Bank in altera DE1 CycloneII the value of Vccio for that IO bank changed from 3.3 v to 2.5v

what is the reason and which value should i consider for my design?

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The LVDS buffers need to be powered at 2.5V to operate within the designed specification. So if you have some LVDS pins in a bank, its VCCIO must be 2.5V.

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i want to know how analoge signal to digital signal.2.5 v will be 0 and 3.5v ill be 1

when p signal > n signal --> 1

when p signal < n signal --> 0

how much difference is considered 1 or 0?

If output, refer to VOD.

If input, refer to VID.

Example: VID is 100mV. That means the p>n by 100mV is considered "1"