Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

check the verilog code of ADC on FPGA

hi all when i assign LVDS pins to one IO Bank in altera DE1 CycloneII the value of Vccio for that IO bank changed from 3.3 v to 2.5v what is the reason and which value should i consider for my d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

hi all

when i assign LVDS pins to one IO Bank in altera DE1 CycloneII the value of Vccio for that IO bank changed from 3.3 v to 2.5v

what is the reason and which value should i consider for my design?