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Altera_Forum
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13 years ago

check the verilog code of ADC on FPGA

hi all when i assign LVDS pins to one IO Bank in altera DE1 CycloneII the value of Vccio for that IO bank changed from 3.3 v to 2.5v what is the reason and which value should i consider for my d...
Altera_Forum's avatar
Altera_Forum
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10 years ago

when p signal > n signal --> 1

when p signal < n signal --> 0

how much difference is considered 1 or 0?

If output, refer to VOD.

If input, refer to VID.

Example: VID is 100mV. That means the p>n by 100mV is considered "1"