Altera_Forum
Honored Contributor
8 years agochanging output from two always blocks
I'm new to verilog so please forgive any ignorance:
i'm using the vga_adapter module which for the purpose of this question just requires an x and y value I use two always blocks to do the math and get the values i want: reg [7:0] x0,y0 and reg [7:0] x1,y1 from always block 1 and 2 respectively, how would I code something such that the vga_adapter gets x0,y0 if write_en = 1, or else x1,y1