Forum Discussion
Honored ContributorCarry Chain used as delay line - Problems with supllying LUT-s with ones and zeros
I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "START" goes high, signal starts to propagate through chain and in moment when STOP occurs, propagation is sampled by registers. To do so, all it takes is to set all the bits of the first operand (input a) to ‘1’ and the bits of the second operand to ‘0’ (input b). Code which works fine for me is :
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity DelayLine is generic ( DATA_WIDTH : natural := 20 ); port ( output: out signed ((DATA_WIDTH-1) downto 0); a: in signed ((DATA_WIDTH-1) downto 0); b: in signed ((DATA_WIDTH-1) downto 0); START: in std_logic ); end DelayLine; architecture rtl of DelayLine is SIGNAL reg: signed ((DATA_WIDTH-1) downto 0); SIGNAL buf: signed ((DATA_WIDTH-1) downto 0); SIGNAL STOP: std_logic; SIGNAL I: integer := 0; begin process (START) variable s : signed ((DATA_WIDTH) downto 0); begin s := ('0' & a) + ('0' & b) + ('0' & START); buf<=s((DATA_WIDTH-1) downto 0); if (falling_edge(START)) then output<=buf((DATA_WIDTH-1) downto 0); end if; end process; end rtl; PROBLEM: Currently my only idea how to supply every adder block with two required signals ('1' and '0') is to make another two registers; one register with ones and other with zeros. Such solution is making a lots of problems in my design. My question is it possible to make some more simple circuit which will supply adders with ones and zeros. I have tried with nonsequential registers (All elements forced to high or low state) but then my carry chain gets deformation.37 Replies
Altera_ForumYeah my method of testing is not the finest :). Actually I have connected first 8 outputs from delay line to the LEDs on board, so idea was to slightly increase phase between two signals (Increase of measurement interval) and watch how far signal has came. This was idea just for seeing if delay line is working. When line will work and thermometer code will be decoded I will send it through SPI to DSP. I think you are absolutely right about STOP and START and how it should be preformed in one cycle. I will surly try to implement your suggestions in my testbench.
- Altera_Forum
No way your eye will register thermometer data if not hold for a while :-) Then you may automate start-stop cycles as often as you like, just use variable freq for testbench reset signal... Let me know about your result and how did you implement the TDC line after all...
- Altera_Forum
No :) you have understand it wrong. Here is how my testbench works: I have two phase shifted signals and here is how START and STOP signals are formed:
https://www.alteraforum.com/forum/attachment.php?attachmentid=12141 When STOP signal rises data is latched and you can see how far signal has propagated. After that START signal goes down and delay line is reset and ready for new cycle of measurement while data is latched and saved. For delay line I use structure of full adders , this method is described in following paper which you can find on this link: https://webcache.googleusercontent.com/search?q=cache:xmqa13wf6n8j:https://www.thinkmind.org/download.php%3farticleid%3dsensorcomm_2015_2_20_10046+&cd=2&hl=hr&ct=clnk&gl=hr&client=opera Idea is to make dynamic phase shift for example with 100 ps step and look TDC behaviour. I have make some tests and I haven't seen anything that looks like delay line is working. I need to increase phase shift to around 400 ps to see some changes in delay line but changes are weird and nothing I would expect. I need to do some more testing and see what I am doing wrong. - Altera_Forum
Yeah, I think I understood correctly, just what I was thinking is that signals run continuously :-)
I know that paper, is one from my list I selected for guidance. Now let's see how two newbie will handle this issue :-) - Altera_Forum
I was exploring about routing in my design and here is what I have found:
https://www.alteraforum.com/forum/attachment.php?attachmentid=12153 Obviously path from my START block to the start of delay line generates delay which is probably part of reason why my TDC doesn't work. I need to explore how this problematic routing can be solved. - Altera_Forum
I would suggest you to reserve by logiclock the required region size for your start block and place it close to the beginning of tdc line, what you need is to have both start and stop signals with same delay...
- Altera_Forum
Possible you may do this, by using start stop two phased clocks, just make sure your testing clock half period is long enough to cover your tdc total delay time, i.e. testing clock should be quite low in its frequency... Then you need to read and save the data for further analysis at the test clock rate...
- Altera_Forum
I think there is no way to control the delay from FPGA pin to delay-line. So the only thing you need to do it to ignore that distance delay. Try to cut it off from your "TDC".
- Altera_Forum
yep, that was my point too, to have both signals at the delay line entry with the required time difference, it does not matter how much time they spend to arrive there, any way the result is taken from the tdc register...
- Altera_Forum
I have a question about the input of TDC, which are implemented inside FPGA. How do you ensure the signal's quality when the trigger input thru the FPGA pin. I mean...when the your start or stop trigger across fpga pin, is there any effect on it? For example expanding the rising time of the start or stop pulse.
Especially, if there are multiple channels, the different fpga pins make same effect on those pulse signals?
