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Altera_Forum
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10 years ago

Carry Chain used as delay line - Problems with supllying LUT-s with ones and zeros

I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "START" goes high, signal starts to pro...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

I was exploring about routing in my design and here is what I have found:

https://www.alteraforum.com/forum/attachment.php?attachmentid=12153

Obviously path from my START block to the start of delay line generates delay which is probably part of reason why my TDC doesn't work. I need to explore how this problematic routing can be solved.