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Altera_Forum
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10 years ago

Carry Chain used as delay line - Problems with supllying LUT-s with ones and zeros

I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "START" goes high, signal starts to pro...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

I have a question about the input of TDC, which are implemented inside FPGA. How do you ensure the signal's quality when the trigger input thru the FPGA pin. I mean...when the your start or stop trigger across fpga pin, is there any effect on it? For example expanding the rising time of the start or stop pulse.

Especially, if there are multiple channels, the different fpga pins make same effect on those pulse signals?