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Altera_Forum
Honored Contributor
10 years agoCarry Chain used as delay line - Problems with supllying LUT-s with ones and zeros
I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "START" goes high, signal starts to pro...
Altera_Forum
Honored Contributor
10 years agoYeah, I think I understood correctly, just what I was thinking is that signals run continuously :-)
I know that paper, is one from my list I selected for guidance. Now let's see how two newbie will handle this issue :-)