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Honored Contributor
Honored ContributorCarry Chain used as delay line - Problems with supllying LUT-s with ones and zeros
I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "START" goes high, signal starts to pro...
Altera_ForumHonored Contributor
Honored ContributorNo :) you have understand it wrong. Here is how my testbench works: I have two phase shifted signals and here is how START and STOP signals are formed:
https://www.alteraforum.com/forum/attachment.php?attachmentid=12141 When STOP signal rises data is latched and you can see how far signal has propagated. After that START signal goes down and delay line is reset and ready for new cycle of measurement while data is latched and saved. For delay line I use structure of full adders , this method is described in following paper which you can find on this link: https://webcache.googleusercontent.com/search?q=cache:xmqa13wf6n8j:https://www.thinkmind.org/download.php%3farticleid%3dsensorcomm_2015_2_20_10046+&cd=2&hl=hr&ct=clnk&gl=hr&client=opera Idea is to make dynamic phase shift for example with 100 ps step and look TDC behaviour. I have make some tests and I haven't seen anything that looks like delay line is working. I need to increase phase shift to around 400 ps to see some changes in delay line but changes are weird and nothing I would expect. I need to do some more testing and see what I am doing wrong.
