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Honored Contributor
Honored ContributorCarry Chain used as delay line - Problems with supllying LUT-s with ones and zeros
I am trying to implement carry chain with Cyclone IV FPGA. I will use carry chain as delay line so here is quick explanation of my program: When input signal "START" goes high, signal starts to pro...
Altera_ForumHonored Contributor
Honored ContributorPossible you may do this, by using start stop two phased clocks, just make sure your testing clock half period is long enough to cover your tdc total delay time, i.e. testing clock should be quite low in its frequency... Then you need to read and save the data for further analysis at the test clock rate...
