Cannot create component from template interface in Platform Designer
Hi!
i try to create a component into Platform designer which includes an interface in system Verilog.
I get the error "Error: Verilog HDL or VHDL XML Interface error at apescore.sv(15): port "i" has an unsupported type File: d:/.....sv Line: 15"
Synthesis works fine.
in order to reproduce the issue you can try the template by:
right click on empty .sv->insertTemplate->Contruct->DesignUnit->Interfaces->masterSlaveExample
This template has an issue with the generic interface, but once you fix that, it gives the same error when you try to create a component.
What is unsupported? Is there a workaround?
thanks
Ioannis
Quartus Standard has limited support in SystemVerilog and you can check the Quartus Prime Standard Edition Help version > Quartus Prime Support for SystemVerilog, for the list of supported constructs.
Do note that you need to install the Intel® Quartus® Prime Help to access it.
KDB Link: https://www.intel.com/content/www/us/en/support/programmable/articles/000097917.html
For Quartus Pro, you can check it online.
Regards,
Richard Tan