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New ContributorCannot create component from template interface in Platform Designer
Hi! i try to create a component into Platform designer which includes an interface in system Verilog. I get the error "Error: Verilog HDL or VHDL XML Interface error at apescore.sv(15): port "i" ha...
Quartus Standard has limited support in SystemVerilog and you can check the Quartus Prime Standard Edition Help version > Quartus Prime Support for SystemVerilog, for the list of supported constructs.
Do note that you need to install the Intel® Quartus® Prime Help to access it.
KDB Link: https://www.intel.com/content/www/us/en/support/programmable/articles/000097917.html
For Quartus Pro, you can check it online.
Regards,
Richard Tan
