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Altera_Forum's avatar
Altera_Forum
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15 years ago

can some onehelp me????

hi everyone .Im a 21 year old girl from Vietnam. i have a project and have to submit it to my teacher on the 20th of May . Can you guys here help me with this project.

I would really appriciate your help^^^

the project is: design and test 4X4 bit unsigned multiplier using right shift add algorithm.

I have difficluties in describing the two registers. Can you help me write it in VHDL code? thanks very much!!!

I have attached the diagram bellow..

Hope to get nice reply from you soon:)

thanks in advance^^^

18 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    dear friend Tricky !

    first of all, thanks for your relpy.

    I have written the code for : mux( 4 bit), adder(4 bit)(it's easier than the rest).Can you help me with : 1 bit right shift-reg, and the 8 bit two registers.

    I understand right shift add algorithm however have difficulties in describing them in VHDL.

    here is my logic( hope it will help you a little bit):

    first: the shift- reg: it has 2 inputs and one output. after 1 clk it performs 1 bit right shift .

    second: the 4 bit MUx: it has 3 inputs,1 output.let's call opc is the signal between the MUx and shift-reg: if opc=1 then opa=multiplicand otherwise opa=0.

    third:the 4 bit adder: 2 inputs(opa,opb) and 2 outputs(cout,sum).

    finally is the 8 bit 2registers. i get troubles with them.

    Is my understand right?

    with little knowledge about VHDL. Hope you can help me as much as possible!!!!

    I have attched one example (word file:23.5k) bellow

    expect to here from you soon friend:-P^^
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi,

    If it helps, I know of another algorithm for multiplication using right shift.

    you add A + B as follows:

    1) if register(0) = '1' then add "B"&"0000" to "0000"&A (8 bit register)

    2) right shift reg result

    repreat above 4 times. take result from shift reg. thats all

    here is the code, checked quickly but not tested well 

    
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mult1 is
port(
     load   : in  std_logic;
     clk    : in  std_logic;
     A      : in  std_logic_vector(3 downto 0);
     B      : in  std_logic_vector(3 downto 0);
     ready  : out std_logic;
     R      : out std_logic_vector(7 downto 0)
     );
end entity;
architecture rtl of mult1 is
signal shift_reg : std_logic_vector(7 downto 0) := x"00";
signal count : integer range 0 to 8 := 0;
begin
process(load,clk)
begin
if load = '1' then
   ready <= '0';
   count <= 0;
   shift_reg <= "0000" & A;
elsif rising_edge(clk) then
 
   if count < 8 then
      count <= count + 1;
   end if;
   
   if count = 8 then
       R <= shift_reg;
       ready <= '1';
   end if;
case count is
    when 0 | 2 | 4 | 6 =>
      if shift_reg(0) = '1' then
         shift_reg <= std_logic_vector(unsigned(shift_reg) +  unsigned(B&"0000"));
      end if;
    
    when 1 |3 | 5 | 7  =>
       shift_reg <= '0' & shift_reg(7 downto 1);
       
    when others => null;
 end case;
 end if;
 end process;
 
end rtl;
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    thanks very much for your help. I need a little time to undertand if it works out for my project.

    really appreciate!!!:p
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I just noted a bug i it.

    It works up to 15 x 8 = 120

    if B is more than 8 it breaks, so needs some debugging if you want to adopt this approach. It is based on old logic of the 70s
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    sorry Kaz.Can you write the algorithm as I have explained above(like in the diagram).bcoz the code must be written in steps that involve components such as : 1 bit shift-reg, Mux(4 bit), adder(4 bit),and the 8 bit registers. Any other solutions? thanks:p

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi,

    Just to debugg my code, the error was due to adder overflow. So I added one more bit. see coe below.

    Meanwhile, I will look at your algorithm and see if I can go further. 

    
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mult1 is
port(
     load   : in  std_logic;
     clk    : in  std_logic;
     A      : in  std_logic_vector(3 downto 0);
     B      : in  std_logic_vector(3 downto 0);
     ready  : out std_logic;
     R      : out std_logic_vector(7 downto 0)
     );
end entity;
architecture rtl of mult1 is
signal shift_reg : std_logic_vector(8 downto 0) := '0'&x"00";
signal count : integer range 0 to 8 := 0;
begin
process(load,clk)
begin
if load = '1' then
   ready <= '0';
   count <= 0;
   shift_reg <= '0'& "0000" & A;
elsif rising_edge(clk) then
 
   if count < 8 then
      count <= count + 1;
   end if;
   
   if count = 8 then
       R <= shift_reg(7 downto 0);
       ready <= '1';
   end if;
case count is
    when 0 | 2 | 4 | 6 =>
      if shift_reg(0) = '1' then
         shift_reg <= std_logic_vector(unsigned(shift_reg) +  unsigned(B&"0000"));
      end if;
    
    when 1 |3 | 5 | 7  =>
       shift_reg <= '0' & shift_reg(8 downto 1);
       
    when others => null;
 end case;
 end if;
 end process;
 
end rtl;
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I now strongly believe, your algorithm is same as mine. In my case I do all in the shift register with no intermediate containers.

    The mux is the test I do on regiser bit(0). The last bit I added was the carry bit.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    thanks for your useful help kaz. Im third year student from Vietnam and now is 6 pm it's time for dinner. Tonight I will try your method and to understand it thorouly.

    if I need your help again. Would you pleased to help me?

    see you tomorrow at the same time.ok.:-P
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I will try but tomorrow this time I will be at work and don't want to upset my boss. I will try today to see if I can really understand and then implement your version as it is blockwise. Enjoy your dinner...