Honored Contributor
Honored ContributorHi,
Just to debugg my code, the error was due to adder overflow. So I added one more bit. see coe below. Meanwhile, I will look at your algorithm and see if I can go further.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mult1 is
port(
load : in std_logic;
clk : in std_logic;
A : in std_logic_vector(3 downto 0);
B : in std_logic_vector(3 downto 0);
ready : out std_logic;
R : out std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of mult1 is
signal shift_reg : std_logic_vector(8 downto 0) := '0'&x"00";
signal count : integer range 0 to 8 := 0;
begin
process(load,clk)
begin
if load = '1' then
ready <= '0';
count <= 0;
shift_reg <= '0'& "0000" & A;
elsif rising_edge(clk) then
if count < 8 then
count <= count + 1;
end if;
if count = 8 then
R <= shift_reg(7 downto 0);
ready <= '1';
end if;
case count is
when 0 | 2 | 4 | 6 =>
if shift_reg(0) = '1' then
shift_reg <= std_logic_vector(unsigned(shift_reg) + unsigned(B&"0000"));
end if;
when 1 |3 | 5 | 7 =>
shift_reg <= '0' & shift_reg(8 downto 1);
when others => null;
end case;
end if;
end process;
end rtl;
