can some onehelp me????

Hi,

If it helps, I know of another algorithm for multiplication using right shift.

you add A + B as follows:

1) if register(0) = '1' then add "B"&"0000" to "0000"&A (8 bit register)

2) right shift reg result

repreat above 4 times. take result from shift reg. thats all

here is the code, checked quickly but not tested well

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mult1 is
port(
     load   : in  std_logic;
     clk    : in  std_logic;
     A      : in  std_logic_vector(3 downto 0);
     B      : in  std_logic_vector(3 downto 0);
     ready  : out std_logic;
     R      : out std_logic_vector(7 downto 0)
     );
end entity;
architecture rtl of mult1 is
signal shift_reg : std_logic_vector(7 downto 0) := x"00";
signal count : integer range 0 to 8 := 0;
begin
process(load,clk)
begin
if load = '1' then
   ready <= '0';
   count <= 0;
   shift_reg <= "0000" & A;
elsif rising_edge(clk) then
 
   if count < 8 then
      count <= count + 1;
   end if;
   
   if count = 8 then
       R <= shift_reg;
       ready <= '1';
   end if;
case count is
    when 0 | 2 | 4 | 6 =>
      if shift_reg(0) = '1' then
         shift_reg <= std_logic_vector(unsigned(shift_reg) +  unsigned(B&"0000"));
      end if;
    
    when 1 |3 | 5 | 7  =>
       shift_reg <= '0' & shift_reg(7 downto 1);
       
    when others => null;
 end case;
 end if;
 end process;
 
end rtl;