can some onehelp me????

dear friend Tricky !

first of all, thanks for your relpy.

I have written the code for : mux( 4 bit), adder(4 bit)(it's easier than the rest).Can you help me with : 1 bit right shift-reg, and the 8 bit two registers.

I understand right shift add algorithm however have difficulties in describing them in VHDL.

here is my logic( hope it will help you a little bit):

first: the shift- reg: it has 2 inputs and one output. after 1 clk it performs 1 bit right shift .

second: the 4 bit MUx: it has 3 inputs,1 output.let's call opc is the signal between the MUx and shift-reg: if opc=1 then opa=multiplicand otherwise opa=0.

third:the 4 bit adder: 2 inputs(opa,opb) and 2 outputs(cout,sum).

finally is the 8 bit 2registers. i get troubles with them.

Is my understand right?

with little knowledge about VHDL. Hope you can help me as much as possible!!!!

I have attched one example (word file:23.5k) bellow

expect to here from you soon friend:-P^^