can some onehelp me????

hi Kaz . iam just back.

Hi,

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mult1 is
port(
     load   : in  std_logic;
     clk    : in  std_logic;
     A      : in  std_logic_vector(3 downto 0);
     B      : in  std_logic_vector(3 downto 0);
     ready  : out std_logic;
     R      : out std_logic
     );
end entity;
architecture rtl of mult1 is
signal shift_reg1 : std_logic_vector(3 downto 0) := "0000";
signal shift_reg2 : std_logic_vector(7 downto 0) := x"00";
signal reg1 : std_logic_vector(7 downto 0);
signal opA : std_logic_vector(3 downto 0);
signal count : integer range 0 to 7 := 0;
begin
R <= shift_reg2(0);
ready <= '1' when count = 5 else '0';
reg1(7 downto 3) <= std_logic_vector(resize(unsigned(OpA),5) +  unsigned(shift_reg2(7 downto 4)));
reg1(2 downto 0) <= shift_reg2(3 downto 1);
process(load,clk)
begin
if load = '1' then
   count <= 0;
   shift_reg1 <= A; -- load input A into shift register
elsif rising_edge(clk) then
   if count < 7 then
      count <= count + 1;
   end if;
   shift_reg1 <= '0' & shift_reg1(3 downto 1); -- shift right
   shift_reg2 <= reg1;
   if shift_reg1(0) = '1' then
       OpA <= B;
   else 
       OpA <= "0000";
   end if;
end if;
end process;
 
end rtl; 
        
   
        

wow! Kaz ,im grateful to you for being so kind to me.I still have 5 days before having to submit my project to my teacher . tomorrow afternoon , I have a test ahead so have to spend time for it. Dont have enough time studying my project right now.

hey Kaz do you have time?

i have difficulties understand your code.

yes plenty of time. which part of code is the difficult?

architecture rtl of mult1 is

Im not very good at VHdl so the question I asked you seem a little '' stupid" .Hope you won;t despise me........