can some onehelp me????

architecture rtl of mult1 is

signal shift_reg1 : std_logic_vector(3 downto 0) := "0000";

signal shift_reg2 : std_logic_vector(7 downto 0) := x"00";

signal reg1 : std_logic_vector(7 downto 0);

signal opA : std_logic_vector(3 downto 0);

begin

R <= shift_reg2(0);

reg1(7 downto 3) <= std_logic_vector(resize(unsigned(OpA),5) + unsigned(shift_reg2(7 downto 4)));

reg1(2 downto 0) <= shift_reg2(3 downto 1);

what's the three signals shift-reg1,shift-reg2,reg1( they are the singals between?) what does shift-reg2(0) mean?

Is it nessecary to write :="0000" and :=x"00" at the signal shift-reg1,2

(My teacher dont write them in the signal declaration)

and the next code I almost don't understand ( other ways to write them easier to understand??).