JKuba2
New Contributor
New ContributorBUG REPORT: VHDL 2008 target aggregate assignment leads to missing driver Warning
Hello,
I'm using target aggregates in VHDL 2008 and I found out, that Quartus (specifically "Quartus Prime Version 19.4.0 Build 64 12/04/2019 SC Pro Edition") fails to assign drivers to some of the target signals when they are std_logic_vector with the width of 1.
Here is an example code I tested it on:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity EXAMPLE is
generic(
WIDTH : natural := 8
);
port(
IN_A : in std_logic_vector(WIDTH-1 downto 0);
IN_B : in std_logic_vector(WIDTH-1 downto 0);
OUT_A : out std_logic_vector(WIDTH-1 downto 0);
OUT_B : out std_logic;
OUT_C : out std_logic_vector(WIDTH-1 downto 0);
OUT_D : out std_logic_vector(1-1 downto 0);
OUT_E : out std_logic_vector(WIDTH/3-1 downto 0);
OUT_F : out std_logic_vector(1-1 downto 0);
OUT_G : out std_logic_vector(2-1 downto 0);
OUT_H : out std_logic_vector(0-1 downto 0);
OUT_I : out std_logic_vector((WIDTH+1)-(WIDTH/3+1+2+0)-1 downto 0)
);
end entity;
architecture FULL of EXAMPLE is
signal result : unsigned(WIDTH+1-1 downto 0);
begin
my_process : process (all)
begin
result <= ("0" & unsigned(IN_A)) + ("0" & unsigned(IN_B));
(OUT_A, OUT_B) <= std_logic_vector(result);
(OUT_C, OUT_D) <= std_logic_vector(result);
(OUT_E, OUT_F, OUT_G, OUT_H, OUT_I) <= std_logic_vector(result);
end process;
end architecture;Synthesizing this code leads to a warning:
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "OUT_D[0]" is stuck at GND File: example.vhd Line: 17
Warning (13410): Pin "OUT_F[0]" is stuck at GND File: example.vhd Line: 20meaning Quartus was unable to assign value to those parts of the aggregate, where the signal had a 1-bit width. You can see, that the bug does not occur, when the signal is a simple std_logic, but I have multiple cases where the width of the signal is determined by generics and it is possible for it to result as 1.
Thanks
