Forum Discussion
Are you saying it's done on purpose and you don't plan on fixing it?
Because it would be a much lesser complication even if it was the other way around and the expression didn't work for std_logic instead. Than I can imagine turning all std_logic signals that are used in aggregates into 1-bit vectors; but this way it cannot be done so easily, since a vector with generic width can sometimes by 1 bit wide and sometimes wider. So the only way to solve this would be creating a std_logic version of each std_logic_vector and switch between them in separated IF branches based on the vector width. And since there are N signals in the aggregate, it would mean up to 2**N different branches of code to solve this. That really makes the whole point of target aggregates being used for code simplification useless.
Sincerely,
JKuba2