Forum Discussion
KhaiChein_Y_Intel
Regular Contributor
5 years agoHi,
Yes. I have reported this to the developer and this is scheduled to be fix in the future release.
Thanks.
Best regards,
KhaiY
- JKuba25 years ago
New Contributor
Thank you very much.
JKuba2
- SSilu5 years ago
New Contributor
I also confirm this annoying bug. It's shame quartus is lacking such basic support of VHDL 2008 features. I took me a few days to find out why my design was not working. Today I also realized that conditional assignment in process VHDL 2008 feature is not working. Quartus simply synthesize logic away.
rx_pkt_len_proc : process(clk_avmm) is begin if rising_edge(clk_avmm) then ready <= '1'; ready <= '0' when ready = '1'; end if; end process;